Semiconductor device manufacturing requires various processes for a semiconductor body including material deposition, removal, patterning, and modification of electrical properties of the semiconductor body. Some of these processes are carried out at high temperatures, for example epitaxial growth and annealing. Processing the semiconductor body at high temperatures generates thermal gradients within the semiconductor body leading to mechanical stress. The semiconductor body may react to thermal stress exceeding a certain threshold value by altering its crystal structure to release the stress, for example by shifting crystal planes relative to each other along preferred crystal lattice planes. This leads to a local disruption of the lattice accompanied by crystal defects such as slip lines. Slip lines may be detrimental to the performance of electrical devices, for example due to an increase of leakage currents caused by the slip lines. With increasing wafer size the problem of crystal defect generation caused by wafer processing such as front-end-of-line (FEOL) processing becomes even more challenging.
It is desirable to increase the mechanical stability of a semiconductor wafer and to provide a method of manufacturing a semiconductor wafer having improved mechanical stability.